Optimizing Bi-layer Lift-off Resist Processes for Insulator Films

The bi-layer lift-off method has been used successfully to commercially fabricate many structures including source, drain ohmic contacts, gates and air bridges for use in Gallium Arsenide (GaAs), GaN, InP, MEMS and other semiconductor devices. It is widely adopted for common pattern metallization processes. The process utilizes LOR PMGI (polydimethylglutarimide) plus an imaging resist to create a dual layer masking structure. Uniquely, this structure can be customized because its composition and dimensions can be tailored for a given material-deposition application system. This is enabling for use in select process applications.
Deployment of VCSEL applications enabled by 5G latency advantages can benefit by using commercialized
technology to comply industry development clock speed. VCSEL devices can be broadly categorized in terms of
deposition material thicknesses and structures based on power output. This study quantifies the most relevant bilayer structural features for effective use with the reference metallization film, Aluminium. It builds on these findings to explore the multivariate optimization required to successfully use bi-layer processing with common metal oxide insulators (SiO2 / Al2O3) in isotropically sputter deposited thicknesses of 100nm to 250nm. A model is presented that characterizes the key variables. Also, it introduces a new high temperature bi-layer process using a negative imaging resist capable of maintaining stability during higher temperature insulator deposition. This investigation identifies the dimensional targets to fabricate successful bi-layer’s for use with sputtered  insulators suitable for process optimization to facilitate evolving IIIV applications.